UVM design functional verification of Advanced Peripheral Bus

Abstract

In hardware design, functional verification identifies the design mistake descriptions that design engineers deliver. To check the functionality, see if the output matches the expected value, and then modify the design to achieve the DUT (Device under Test) required functionality. The Advanced Peripheral Bus (APB) execution protocol links the peripherals through transport customs. ABP has poor data moving capacity and low data transfer volume. These test cases cover manifold write transactions with and without wait states, multiple read and write transactions with and without a wait state, and single and multiple write transactions with and without a wait. The design was programmed using Verilog HDL and testing was verified on a Verilog test bench. The master and slave mode operation is carried out in which the master sends a packet containing the slave's addresses and control signal to the slave. In the consequences, they comprise the slave's addresses and a control signal to the slave, as they are equivalent. Later, it receives a write-and-read data transaction in which the master provides the address, and then the slave identifies it and transmits it to the master as read data. The APB protocol structure is verified using UVM for applications in ASIC (Application Specific Integrated Circuits) or SOC (System on Chip) configurations.